HARDWARE IMPLEMENTATION OF AN ANALOG SPIKING NEURON WITH DIGITAL CONTROL OF INPUT SIGNALS WEIGHING
DOI:
https://doi.org/10.15588/1607-3274-2024-4-9Keywords:
neuromorphic processor, spiking neural network, neuron, synaptic coefficient, layout designAbstract
Context. Significant challenges facing hardware developers of artificial intelligence systems force them to look for new nonstandard architectural solutions. One of the promising solutions is the transition from von Neumann’s classic architecture to neuromorphic architecture, which at the hardware level tries to imitate the work of the neural network of the human brain. A neuromorphic processor built as hardware implementation of a spiking neural network consists of a large number of elementary electronic circuits that structurally and functionally correspond to neurons. Thus, the design of hardware implementation of a spiking neuron as the basic building element of a neuromorphic processor is of great scientific interest.
Objective. The goal of the work is to design an analog spiking neuron hardware implementation with digital control of input signals by binary synaptic weighting coefficients.
Method. Designing is performed at the logical/schematic and topological levels of the design flow using modern tools of electronic design automation. All proposed schematic and layout solutions are verified and simulated using computer aided design tools to prove their functionality.
Results. The schematic and layout solutions have been developed and investigated for the hardware implementation of the spiking analog neuron with digital control of input signals by binary synaptic weighting coefficients to be the basic building element of a spiking neural network of the neuromorphic processor.
Conclusions. The proposed hybrid design of the spiking neuron hardware implementation benefits by combining the simplicity of analog signal processing methods in the neuron with digital control of the state of the neuron using binary weighting coefficients. The simulation results confirm the functionality of the obtained schematic/layout solutions and demonstrate the possibility of implementing logical functions inherent in the perceptron. The prospects for further research may include the design of hardware implementation for a spiking neural network core based on the developed schematic and layout solutions for the spiking neuron.
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