MECHANISMS OF SCHEMATIC MODELING BASED ON VECTOR LOGIC

Abstract

Context. This paper addresses issues relevant to the EDA market – reducing the cost and time of testing and verification of digital projects by synthesizing the logic vector of a digital circuit, which significantly simplifies the algorithms of good-value simulation and reduces the synthesis of the test map to three matrix operations.
Objective. The aim of the study is to reduce the cost and time of testing and verification of digital projects by synthesizing the logic vector of a digital circuit, which allows for simplifying the algorithm for constructing the test map to three matrix operations.
Method. The synthesis of a logic vector for a combinational circuit is proposed for good-value and fault as modeling addresses within the architecture of prompt-intelligent in-memory computing. The logic vector is the most technological, compact, and exhaustive representation of the circuit for efficiently solving all design and testing tasks. Cartesian logic is proposed as an effective intelligent mechanism for solving combinatorial problems (modeling, simulation, testing, diagnostics) using algorithms of linear computational complexity, thanks to its exponential redundancy 2 ^n+m . Mechanisms are proposed for constructing a logic vector of a process or phenomenon, function or structure, based on matrix structures of Cartesian logic for solving Modeling for Simulation tasks. An engineering method of direct parallel good-value modeling of the circuit is proposed, based on the use of logic vectors of elements and truth tables. Cartesian logic is a logic vector (matrix) as the result of modeling Cartesian logical relations between the bits of logic vectors or truth table addresses. Cartesian logic solves the following tasks: 1. Good-value modeling of a circuit logic vector without the need for a functional behavior modeling algorithm. 2. Fault modeling testing map of logic without a fault simulation algorithm.                                                  Results. A mathematical apparatus of Cartesian logic is proposed, represented as a logic vector (matrix), which is the result of modeling Cartesian logical relations between the bits of logic vectors or addresses of the truth table. Based on the theory of vector logic, mechanisms and software have been developed for efficiently solving design and test tasks within the in-memory computing architecture.
Conclusions. The practical value of the study lies in addressing all design and test tasks using simple models of vector logic, oriented toward economical in-memory computing based on read-write transactions and free from processor instructions. It is proposed to use the specification logic vector within the in-memory computing architecture for testing, verification, diagnostics, and operation. In-memory vector logic computing is an economical solution to many computational problems in terms of energy, time, and cost efficiency. The novelty of the study lies in the use of vector logic within the in-memory computing architecture based on read-write transactions, which reduces resource consumption in terms of time and energy. Implementing vector logic in in-memory computing makes it scalable and energy-efficient, and frees it from complex big data analysis algorithms.