1.
Mіroshnyk MA, Shkil AS, Kulak EN, Rakhlis DY, Mіroshnyk AM, Malahov NV. DESIGN TIMED FSM WITH VHDL MOORE PATTERN. RIC [Internet]. 2020Sep.8 [cited 2024Nov.29];(2):137-48. Available from: https://ric.zp.edu.ua/article/view/208496